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M28F008 8 MBIT (1 MBIT x 8) FLASH MEMORY
Y
High-Density Symmetrically Blocked Architecture Sixteen 64 Kbyte Blocks Extended Cycling Capability 10K Block Erase Cycles Minimum 160K Block Erase Cycles per Chip Automated Byte Write and Block Erase Command User Interface Status Register System Performance Enhancements RY BY Status Output Erase Suspend Capability SRAM-Compatible Write Interface
Y
Very High-Performance Read 100 ns Maximum Access Time Hardware Data Protection Feature Erase Write Lockout during Power Transitions Industry Standard Packaging 40-Lead Sidebrazed DIP 42-Lead Flatpack ETOX TM Nonvolatile Flash Technology 12V Byte Write Block Erase Independent Software Vendor Support Microsoft Flash File System (FFS)
Y
Y
Y
Y
Y
Y
Y
Y
Intel's M28F008 8-Mbit FlashFile Memory is the highest density nonvolatile read write solution for solid state storage The M28F008's extended cycling symmetrically blocked architecture fast access time write automation and low power consumption provide a more reliable lower power lighter weight and higher performance alternative to traditional rotating disk technology The M28F008 brings new capabilities to portable computing Application and operating system software stored in resident flash memory arrays provide instant-on rapid execute-in-place and protection from obsolescence through in-system software updates Resident software also extends system battery life and increases reliability by reducing disk drive accesses For high-density data acquisition applications the M28F008 offers a more cost-effective and reliable alternative to SRAM and battery Traditional high density embedded applications such as telecommunications can take advantage of the M28F008's nonvolatility blocking and minimal system code requirements for flexible firmware and modular software designs The M28F008 is offered in 40-lead sidebrazed DIP and 42-lead Flatpack packages This device uses an integrated Command User Interface and state machine for simplified block erasure and byte write The M28F008 memory map consists of 16 separately erasable 64 Kbyte blocks Intel's M28F008 employs advanced CMOS circuitry for systems requiring low power consumption and noise immunity Its 100 ns access time provides superior performance when compared with magnetic storage media A deep powerdown mode lowers power consumption to 500 mW maximum thru VCC The RP power control input also provides absolute data protection during system powerup down Manufactured on Intel's ETOX process technology the M28F008 provides the highest levels of quality reliability and cost-effectiveness
Microsoft is a trademark of Microsoft Corporation
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1994
Order Number 271232-004
M28F008
The Status Register indicates the status of the WSM and when the WSM successfully completes the desired byte write or block erase operation The RY BY output gives an additional indicator of WSM activity providing capability for both hardware signal of status (versus software polling) and status masking (interrupt masking for background erase for example) Status polling using RY BY minimizes both CPU overhead and system power consumption When low RY BY indicates that the WSM is performing a block erase or byte write operation RY BY high indicates that the WSM is ready for new commands block erase is suspended or the device is in deep powerdown mode Maximum access time is 100 ns (tACC) over the military temperature range ( b 55 C to a 125 C) and over VCC supply voltage range 4 5V to 5 5V ICC active current (CMOS Read) is 35 mA maximum at 8 MHz When the CE and RP pins are at VCC the ICC CMOS Standby mode is enabled A Deep Powerdown mode is enabled when the RP pin is at GND minimizing power consumption and providing write protection ICC current in deep powerdown is 100 mA maximum Reset time of 400 ns is required from RP switching high until outputs are valid to read attempts Equivalently the device has a wake time of 1 ms from RP high until writes to the Command User Interface are recognized by the M28F008 With RP at GND the WSM is reset and the Status Register is cleared
PRODUCT OVERVIEW
The M28F008 is a high-performance 8 Mbit (8 388 608 bit) memory organized as 1 Mbyte (1 048 576 bytes) of 8 bits each Sixteen 64 Kbyte (65 536 byte) blocks are included on the M28F008 A memory map is shown in Figure 4 of this specification A block erase operation erases one of the sixteen blocks of memory in typically 1 6 seconds independent of the remaining blocks Each block can be independently erased and written 10 000 cycles Erase Suspend mode allows system software to suspend block erase to read data or execute code from any other block of the M28F008 The M28F008 is available in 40-lead sidebrazed DIP and 42-lead Flatpack packages Pinouts are shown in Figures 2a and 2b of this specification The Command User Interface serves as the interface between the microprocessor or microcontroller and the internal operation of the M28F008 Byte Write and Block Erase Automation allow byte write and block erase operations to be executed using a two-write command sequence to the Command User Interface The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for byte write and block erase operations including verifications thereby unburdening the microprocessor or microcontroller Writing of memory data is performed in byte increments typically within 9 ms an 80% improvement over current flash memory products IPP byte write and block erase currents are 30 mA maximum VPP byte write and block erase voltage is 11 4V to 12 6V
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M28F008
271232 - 1
Figure 1 Block Diagram Table 1 Pin Description Symbol A0 -A19 DQ0 -DQ7 Type INPUT INPUT OUTPUT Name and Function ADDRESS INPUTS for memory addresses Addresses are internally latched during a write cycle DATA INPUT OUTPUTS Inputs data and commands during Command User Interface write cycles outputs data during memory array Status Register and Identifier read cycles The data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled Data is internally latched during a write cycle CHIP ENABLE Activates the device's control logic input buffers decoders and sense amplifiers CE is active low CE high deselects the memory device and reduces power consumption to standby levels RESET DEEP POWERDOWN Puts the device in deep powerdown mode RP is active low RP high gates normal operation RP also locks out block erase or byte write operations when active low providing data protection during power transitions RP active resets internal automation Exit from Deep Powerdown sets device to read-array mode OUTPUT ENABLE Gates the device's outputs through the data buffers during a read cycle OE is active low WRITE ENABLE Controls writes to the Command User Interface and array blocks WE is active low Addresses and data are latched on the rising edge of the WE pulse
CE
INPUT
RP
INPUT
OE WE
INPUT INPUT
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M28F008
Table 1 Pin Description (Continued) Symbol RY BY Type OUTPUT Name and Function READY BUSY Indicates the status of the internal Write State Machine When low it indicates that the WSM is performing a block erase or byte write operation RY BY high indicates that the WSM is ready for new commands block erase is suspended or the device is in deep powerdown mode RY BY is always active and does NOT float to tri-state off when the chip is deselected or data outputs are disabled BLOCK ERASE BYTE WRITE POWER SUPPLY for erasing blocks of the array or writing bytes of each block NOTE With VPP k VPPLMAX memory contents cannot be altered DEVICE POWER SUPPLY (5V g10%) GROUND
VPP
VCC GND
271232 - 2
271232 - 14
Figure 2a DIP Pinout
Figure 2b Flatpack Pinout
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M28F008
271232 - 3
Figure 3 M28F008 Array Interface to Intel386 TM SL Microprocessor Superset through PI Bus (Including RY BY Masking and Selective Powerdown) for DRAM Backup during System SUSPEND Resident O S and Applications and Motherboard Solid-State Disk
PRINCIPLES OF OPERATION
The M28F008 includes on-chip write automation to manage write and erase functions The Write State Machine allows for 100% TTL-level control inputs fixed power supplies during block erasure and byte write and minimal processor overhead with RAMlike interface timings After initial device powerup or after return from deep powerdown mode (see Bus Operations) the M28F008 functions as a read-only memory Manipulation of external memory-control pins allow array read standby and output disable operations Both Status Register and intelligent identifier can
also be accessed through the Command User Interface when VPP e VPPL This same subset of operations is also available when high voltage is applied to the VPP pin In addition high voltage on VPP enables successful block erasure and byte writing of the device All functions associated with altering memory contents byte write block erase status and intelligent identifier are accessed via the Command User Interface and verified thru the Status Register Commands are written using standard microprocessor write timings Command User Interface contents serve as input to the WSM which controls the block 5
M28F008
erase and byte write circuitry Write cycles also internally latch addresses and data needed for byte write or block erase operations With the appropriate command written to the register standard microprocessor read timings output array data access the intelligent identifier codes or output byte write and block erase status for verification Interface software to initiate and poll progress of internal byte write and block erase can be stored in any of the M28F008 blocks This code is copied to and executed from system RAM during actual flash memory update After successful completion of byte write and or block erase code data reads from the M28F008 are again possible via the Read Array command Erase suspend resume capability allows system software to suspend block erase to read data and execute code from any other block
Command User Interface and Write Automation
An on-chip state machine controls block erase and byte write freeing the system processor for other tasks After receiving the Erase Setup and Erase Confirm commands the state machine controls block pre-conditioning and erase returning progress via the Status Register and RY BY output Byte write is similarly controlled after destination address and expected data are supplied The program and erase algorithms of past Intel Flash memories are now regulated by the state machine including pulse repetition where required and internal verification and margining of data
Data Protection
Depending on the application the system designer may choose to make the VPP power supply switchable (available only when memory byte writes block erases are required) or hardwired to VPPH When VPP e VPPL memory contents cannot be altered The M28F008 Command User Interface architecture provides protection from unwanted byte write or block erase operations even when high voltage is applied to VPP Additionally all functions are disabled whenever VCC is below the write lockout voltage VLKO or when RP is at VIL The M28F008 accommodates either design practice and encourages optimization of the processor-memory interface The two-step byte write block erase Command User Interface write sequence provides additional software write protection
FFFFF F0000 EFFFF E0000 DFFFF D0000 CFFFF C0000 BFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block
BUS OPERATION
Flash memory reads erases and writes in-system via the local CPU All bus cycles to or from the flash memory conform to standard microprocessor bus cycles
Read
The M28F008 has three read modes The memory can be read from any of its blocks and information can be read from the intelligent identifier or Status Register VPP can be at either VPPL or VPPH The first task is to write the appropriate read mode command to the Command User Interface (array intelligent identifier or Status Register) The M28F008 automatically resets to Read Array mode upon initial device powerup or after exit from deep powerdown The M28F008 has four control pins two of which
Figure 4 Memory Map
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Table 2 Bus Operations Mode Read Output Disable Standby PowerDown Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write 345 Notes 123 3 3 RP VIH VIH VIH VIL VIH VIH VIH CE VIL VIL VIH X VIL VIL VIL OE VIL VIH X X VIL VIL VIH WE VIH VIH X X VIH VIH VIL A0 X X X X VIL VIH X VPP X X X X X X X DQ0-7 DOUT High Z High Z High Z 89H A2H DIN RY BY X X X VOH VOH VOH X
NOTES 1 Refer to DC Characteristics When VPP e VPPL memory contents can be read but not written or erased 2 X can be VIL or VIH for control pins and addresses and VPPL or VPPH for VPP See DC Characteristics for VPPL and VPPH voltages 3 RY BY is VOL when the Write State Machine is executing internal block erase or byte write algorithms It is VOH when the WSM is not busy in Erase Suspend mode or deep powerdown mode 4 Command writes involving block erase or byte write are only successfully executed when VPP e VPPH 5 Refer to Table 3 for valid DIN during a write operation
must be logically active to obtain data at the outputs Chip Enable (CE) is the device selection control and when active enables the selected memory device Output Enable (OE) is the data input output (DQ0 - DQ7) direction control and when active drives data from the selected memory onto the I O bus RP and WE must also be at VIH Figure 8 illustrates read bus cycle waveforms
Output Disable
With OE at a logic-high level (VIH) the device outputs are disabled Output pins (DQ0 -DQ7) are placed in a high-impedance state
read modes RP at a logic-low level (VIL) deselects the memory places output drivers in a high-impedence state and turns off all internal circuits The M28F008 requires time tPHQV (see AC Characteristics-Read-Only Operations) after return from powerdown until initial memory access outputs are valid After this wakeup interval normal operation is restored The Command User Interface is reset to Read Array mode and the upper 5 bits of the Status Register are cleared to value 10000 upon return to normal operation During block erase or byte write modes RP at a logic-low level (VIL) will abort either operation Memory contents of the block being altered are no longer valid as the data will be partially written or erased Time tPHWL after RP goes to logic-high (VIH) is required before another command can be written
Standby
CE at a logic-high level (VIH) places the M28F008 in standby mode Standby operation disables much of the M28F008's circuitry and substantially reduces device power consumption The outputs (DQ0 -DQ7) are placed in a high-impedence state independent of the status of OE If the M28F008 is deselected during block erase or byte write the device will continue functioning and consuming normal active power until the operation completes
Intelligent Identifier Operation
The intelligent identifier operation outputs the manufacturer code 89H and the device code A2H for the M28F008 The system CPU can then automatically match the device with its proper block erase and byte write algorithms The manufacturer and device codes are read via the Command User Interface Following a write of 90H to the Command User Interface a read from address location 00000H outputs the manufacturer code (89H) A read from address location 00001H outputs the device code (A2H) It is not necessary to have high voltage applied to VPP to read the intelligent identifier from the Command User Interface
Deep Power-Down
The M28F008 offers a deep powerdown feature entered when RP is at VIL Current draw thru VCC is 100 mA maximum in deep powerdown mode with current draw through VPP 20 mA maximum During
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M28F008
Table 3 Command Definitions Command Read Array Reset Intelligent Identifier Read Status Register Clear Status Register Erase Setup Erase Confirm Erase Suspend Erase Resume Byte Write Setup Write Alternate Byte Write Setup Write Bus First Bus Cycle Second Bus Cycle Cycles Notes Req'd Operation Address Data Operation Address Data 1 3 2 1 2 2 2 2 235 235 2 1 234 3 Write Write Write Write Write Write Write Write X X X X BA X WA WA FFH 90H 70H 50H 20H B0H 40H 10H Write Write Write Write BA X WA WA D0H D0H WD WD Read Read IA X IID SRD
NOTES 1 Bus operations are defined in Table 2 2 IA e Identifier Address 00H for manufacturer code 01H for device code BA e Address within the block being erased WA e Address of memory location to be written 3 SRD e Data read from Status Register See Table 4 for a description of the Status Register bits WD e Data to be written at location WA Data is latched on the rising edge of WE IID e Data read from intelligent identifiers 4 Following the intelligent identifier command two read operations access manufacture and device codes 5 Either 40H or 10H are recognized by the WSM as the Byte Write Setup command 6 Commands other than those shown above are reserved by Intel for future device implementations and should not be used
Write
Writes to the Command User Interface enable reading of device data and intelligent identifier They also control inspection and clearing of the Status Register Additionally when VPP e VPPH the Command User Interface controls block erasure and byte write The contents of the interface register serve as input to the internal write state machine The Command User Interface itself does not occupy an addressable memory location The interface register is a latch used to store the command and address and data information needed to execute the command Erase Setup and Erase Confirm commands require both appropriate command data and an address within the block to be erased The Byte Write Setup command requires both appropriate command data and the address of the location to be written while the Byte Write command consists of the data to be written and the address of the location to be written The Command User Interface is written by bringing WE to a logic-low level (VIL) while CE is low Addresses and data are latched on the rising edge of WE Standard microprocessor write timings are used
Refer to AC Write Characteristics and the AC Waveforms for Write Operations Figure 9 for specific timing parameters
COMMAND DEFINITIONS
When VPPL is applied to the VPP pin read operations from the Status Register intelligent identifier or array blocks are enabled Placing VPPH on VPP enables successful byte write and block erase operations as well Device operations are selected by writing specific commands into the Command User Interface Table 3 defines the M28F008 commands
Read Array Command
Upon initial device powerup and after exit from deep powerdown mode the M28F008 defaults to Read Array mode This operation is also initiated by writing FFH into the Command User Interface Microprocessor read cycles retrieve array data The device remains enabled for reads until the Command User Interface contents are altered Once the internal Write State Machine has started a block erase or byte write operation the device will not recognize
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M28F008
Table 4 Status Register Definitions
WSMS 7
ESS 6
ES 5
BWS 4
VPPS 3
R 2
R 1
R 0
SR 7 e WRITE STATE MACHINE STATUS 1 e Ready 0 e Busy SR 6 e ERASE SUSPEND STATUS 1 e Erase Suspended 0 e Erase in Progress Completed SR 5 e ERASE STATUS 1 e Error in Block Erasure 0 e Successful Block Erase SR 4 e BYTE WRITE STATUS 1 e Error in Byte Write 0 e Successful Byte Write SR 3 e VPP STATUS 1 e VPP Low Detect Operation Abort 0 e VPP OK SR 2-SR 0 e RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use and should be masked out when polling the Status Register
NOTES RY BY or the Write State Machine Status bit must first be checked to determine byte write or block erase completion before the Byte Write or Erase Status bit are checked for success If the Byte Write AND Erase Status bits are set to ``1''s during a block erase attempt an improper command sequence was entered Attempt the operation again If VPP low status is detected the Status Register must be cleared before another byte write or block erase operation is attempted The VPP Status bit unlike an A D converter does not provide continuous indication of VPP level The WSM interrogates the VPP level only after the byte write or block erase command sequences have been entered and informs the system if VPP has not been switched on The VPP Status bit is not guaranteed to report accurate feedback between VPPL and VPPH
the Read Array command until the WSM has completed its operation The Read Array command is functional when VPP e VPPL or VPPH
Intelligent Identifier Command
The M28F008 contains an intelligent identifier operation initiated by writing 90H into the Command User Interface Following the command write a read cycle from address 00000H retrieves the manufacturer code of 89H A read cycle from address 01H returns the device code of A2H To terminate the operation it is necessary to write another valid command into the register Like the Read Array command the intelligent identifier command is functional when VPP e VPPL or VPPH
Command User Interface The contents of the Status Register are latched on the falling edge of OE or CE whichever occurs last in the read cycle OE or CE must be toggled to VIH before further reads to update the Status Register latch The Read Status Register command functions when VPP e VPPL or VPPH
Clear Status Register Command
The Erase Status and Byte Write Status bits are set to ``1''s by the Write State Machine and can only be reset by the Clear Status Register Command These bits indicate various failure conditions (see Table 4) By allowing system software to control the resetting of these bits several operations may be performed (such as cumulatively writing several bytes or erasing multiple blocks in sequence) The Status Register may then be polled to determine if an error occurred during that sequence This adds flexibility to the way the device may be used Additionally the VPP Status bit (SR 3) MUST be reset by system software before further byte writes or block erases are attempted To clear the Status Register the Clear Status Register command (50H) is written to the Command User Interface The Clear Status Register command is functional when VPP e VPPL or VPPH
Read Status Register Command
The M28F008 contains a Status Register which may be read to determine when a byte write or block erase operation is complete and whether that operation completed successfully The Status Register may be read at any time by writing the Read Status Register command (70H) to the Command User Interface After writing this command all subsequent read operations output data from the Status Register until another valid command is written to the
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M28F008
At this point a Read Array command can be written to the Command User Interface to read data from blocks other than that which is suspended The only other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H) at which time the WSM will continue with the erase process The Erase Suspend status and WSM status bits of the Status Register will be automatically cleared and RY BY will return to VOL After the Erase Resume command is written to it the M28F008 automatically outputs Status Register data when read (see Figure 7 Erase Suspend Resume Flowchart) VPP must remain at VPPH while the M28F008 is in Erase Suspend
Erase Setup Erase Confirm Commands
Erase is executed one block at a time initiated by a two-cycle command sequence An Erase Setup command (20H) is first written to the Command User Interface followed by the Erase Confirm command (D0H) These commands require both appropriate sequencing and an address within the block to be erased to FFH Block preconditioning erase and verify are all handled internally by the Write State Machine invisible to the system After the two-command erase sequence is written to it the M28F008 automatically outputs Status Register data when read (see Figure 6 Block Erase Flowchart) The CPU can detect the completion of the erase event by analyzing the output of the RY BY pin or the WSM Status bit of the Status Register When erase is completed the Erase Status bit should be checked If erase error is detected the Status Register should be cleared The Command User Interface remains in Read Status Register mode until further commands are issued to it This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased Also reliable block erasure can only occur when VPP e VPPH In the absence of this high voltage memory contents are protected against erasure If block erase is attempted while VPP e VPPL the VPP Status bit will be set to ``1'' Erase attempts while VPPL k VPP k VPPH produce spurious results and should not be attempted
Byte Write Setup Write Commands
Byte write is executed by a two-command sequence The Byte Write Setup command (40H) is written to the Command User Interface followed by a second write specifying the address and data (latched on the rising edge of WE) to be written The WSM then takes over controlling the byte write and write verify algorithms internally After the two-command byte write sequence is written to it the M28F008 automatically outputs Status Register data when read (see Figure 5 Byte Write Flowchart) The CPU can detect the completion of the byte write event by analyzing the output of the RY BY pin or the WSM status bit of the Status Register Only the Read Status Register command is valid while byte write is active When byte write is complete the Byte Write status bit should be checked If byte write error is detected the Status Register should be cleared The internal WSM verify only detects errors for ``1''s that do not successfully write to ``0''s The Command User Interface remains in Read Status Register mode until further commands are issued to it If byte write is attempted while VPP e VPPL the VPP Status bit will be set to ``1'' Byte write attempts while VPPL k VPP k VPPH produce spurious results and should not be attempted
Erase Suspend Erase Resume Commands
The Erase Suspend command allows block erase interruption in order to read data from another block of memory Once the erase process starts writing the Erase Suspend command (B0H) to the Command User Interface requests that the WSM suspend the erase sequence at a predetermined point in the erase algorithm The M28F008 continues to output Status Register data when read after the Erase Suspend command is written to it Polling the WSM status and Erase Suspend status bits will determine when the erase operation has been suspended (both will be set to ``1'') RY BY will also transition to VOH
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M28F008
Erase typically takes 1 6 seconds per block The Erase Suspend Erase Resume command sequence allows suspension of this erase operation to read data from a block other than that in which erase is being performed A system software flowchart is shown in Figure 7 The entire sequence is performed with VPP at VPPH Abort occurs when RP transitions to VIL or VPP falls to VPPL while erase is in progress Block data is partially erased by this operation and a repeat of erase is required to obtain a fully erased block
EXTENDED BLOCK ERASE BYTE WRITE CYCLING
Intel has designed extended cycling capability into its ETOX flash memory technologies The M28F008 is designed for 10 000 byte write block erase cycles on each of the sixteen 64 Kbyte blocks Low electric fields advanced oxides and minimal oxide area per cell subjected to the tunneling electric field combine to greatly reduce oxide stress and the probability of failure A 20 Mbyte solid-state drive using an array of M28F008s has a MTBF (Mean Time Between Failure) of 3 33 million hours(1) over 600 times more reliable than equivalent rotating disk technology
DESIGN CONSIDERATIONS Three-Line Output Control
The M28F008 will often be used in large memory arrays Intel provides three control inputs to accommodate multiple memory connections Three-line control provides for a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these control inputs an address decoder should enable CE while OE should be connected to all memory devices and the system's READ control line This assures that only selected memory devices have active outputs while deselected memory devices are in Standby Mode Finally RP should either be tied to the system RESET or connected to VCC if unused
AUTOMATED BYTE WRITE
The M28F008 integrates the Quick-Pulse programming algorithm of prior Intel Flash devices on-chip using the Command User Interface Status Register and Write State Machine (WSM) On-chip integration dramatically simplifies system software and provides processor interface timings to the Command User Interface and Status Register WSM operation internal verify and VPP high voltage presence are monitored and reported via the RY BY output and appropriate Status Register bits Figure 5 shows a system software flowchart for device byte write The entire sequence is performed with VPP at VPPH Byte write abort occurs when RP transitions to VIL or VPP drops to VPPL Although the WSM is halted byte data is partially written at the location where byte write was aborted Block erasure or a repeat of byte write is required to initialize this data to a known value
AUTOMATED BLOCK ERASE
As above the Quick-Erase algorithm of prior Intel Flash devices is now implemented internally including all preconditioning of block data WSM operation erase success and VPP high voltage presence are monitored and reported through RY BY and the Status Register Additionally if a command other than Erase Confirm is written to the device following Erase Setup both the Erase Status and Byte Write Status bits will be set to ``1''s When issuing the Erase Setup and Erase Confirm commands they should be written to an address within the address range of the block to be erased Figure 6 shows a system software flowchart for block erase
RY BY and Byte Write Block Erase Polling
RY BY is a full CMOS output that provides a hardware method of detecting byte write and block erase completion It transitions low time tWHRL after a write or erase command sequence is written to the M28F008 and returns to VOH when the WSM has finished executing the internal algorithm RY BY can be connected to the interrupt input of the system CPU or controller It is active at all times not tri-stated if the M28F008 CE or OE inputs are brought to VIH RY BY is also VOH when the device is in Erase Suspend or deep powerdown modes
(1)Assumptions 10 Kbyte file written every 10 minutes (20 Mbyte array) (10 Kbyte file) e 2 000 file writes before erase required (2000 files writes erase) c (10 000 cycles per M28F008 block) e 20 million file writes (20 c 106 file writes) c (10 min write) c (1 hr 60 min) e 3 33 c 106 MTBF
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M28F008
Bus Operation Write
Command Byte Write Setup
Comments Data e 40H (10H) Address e Byte to be written
Write
Byte Write
Data to be written Address e Byte to be written
Standby Read
Check RY BY VOH e Ready VOL e Busy or Read Status Register Check SR 7 1 e Ready 0 e Busy Toggle OE or CE to update Status Register
271232 - 4
Repeat for subsequent bytes Full status check can be done after each byte or after a sequence of bytes Write FFH after the last byte write operation to reset the device to Ready Array Mode
FULL STATUS CHECK PROCEDURE
Bus Operation Optional Read
Command
Comments CPU may already have read Status Register data in WSM Ready polling above Check SR 3 1 e VPP Low Detect
Standby
Standby
Check SR 4 1 e Byte Write Error
SR 3 MUST be cleared if set during a byte write attempt before further attempts are allowed by the Write State Machine
271232 - 5
SR 4 is only cleared by the Clear Status Register Command in cases where multiple bytes are written before full status is checked If error is detected clear the Status Register before attempting retry or other error recovery
Figure 5 Automated Byte Write Flowchart
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M28F008
Bus Operation Write
Command Erase Setup
Comments Data e 20H Address e Within block to be erased Data e D0H Address e Within block to be erased Check RY BY VOH e Ready VOL e Busy or Read Status Register Check SR 7 1 e Ready 0 e Busy Toggle OE or CE to update Status Register
Write
Erase
Standby Read
271232 - 6
Repeat for subsequent bytes Full status check can be done after each block or after a sequence of blocks Write FFH after the last block erase operation to reset the device to Ready Array Mode
FULL STATUS CHECK PROCEDURE
Bus Operation Optional Read
Command
Comments CPU may already have read Status Register data in WSM Ready polling above Check SR 3 1 e VPP Low Detect
Standby
Standby
Check SR 4 5 Both 1 e Command Sequence Error Check SR 5 1 e Block Erase Error
Standby
SR 3 MUST be cleared if set during a block erase attempt before further attempts are allowed by the Write State Machine
271232 - 7
SR 5 is only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked If error is detected clear the Status Register before attempting retry or other error recovery
Figure 6 Automated Block Erase Flowchart
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M28F008
Bus Operation Write
Command Erase Suspend Read Status Register
Comments Data e B0H
Write
Data e 70H
Standby Read
Check RY BY VOH e Ready VOL e Busy or Read Status Register Check SR 7 1 e Ready 0 e Busy Toggle OE or CE to Update Status Register
Standby
Check SR 6 1 e Suspended
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Write
Read Array
Data e FFH
Read
Read array data from block other than that being erased Erase Resume Data e D0H
Write
Figure 7 Erase Suspend Resume Flowchart
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M28F008
After byte write or block erase is complete even after VPP transitions down to VPPL the Command User Interface must be reset to Read Array mode via the Read Array command if access to the memory array is desired
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling System designers are interested in 3 supply current issues standby current levels (ISB) active current levels (ICC) and transient peaks produced by falling and rising edges of CE Transient current magnitudes depend on the device outputs' capacitive and inductive loading Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks Each device should have a 0 1 mF ceramic capacitor connected between each VCC and GND and between its VPP and GND These high frequency low inherent-inductance capacitors should be placed as close as possible to package leads Additionally for every 8 devices a 4 7 mF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND The bulk capacitor will overcome voltage slumps caused by PC board trace inductances
Power Up Down Protection
The M28F008 is designed to offer protection against accidental block erasure or byte writing during power transitions Upon power-up the M28F008 is indifferent as to which power supply VPP or VCC powers up first Power supply sequencing is not required Internal circuitry in the M28F008 ensures that the Command User Interface is reset to the Read Array mode on power up A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active Since both WE and CE must be low for a command write driving either to VIH will inhibit writes The Command User Interface architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences Finally the device is disabled until RP is brought to VIH regardless of the state of its control inputs This provides an additional level of memory protection
VPP Trace on Printed Circuit Boards
Writing flash memories while they reside in the target system requires that the printed circuit board designer pay attention to the VPP power supply trace The VPP pin supplies the memory cell current for writing and erasing Use similar trace widths and layout considerations given to the VCC power bus Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots
Power Dissipation
When designing portable systems designers must consider battery power consumption not only during device operation but also for data retention during system idle time Flash nonvolatility increases usable battery life because the M28F008 does not consume any power to retain code or data when the system is off In addition the M28F008's deep powerdown mode ensures low power dissipation even when system power is applied For example portable PCs and other power sensitive applications using an array of M28F008s for solid-state storage can lower RP to VIL in standby or sleep modes reducing power consumption If access to the M28F008 is again needed the part can again be read following the tPHQV and tPHWL wakeup cycles required after RP is first raised back to VIH See AC Characteristics ReadOnly and Write Operations and Figures 8 and 9 for more information
VCC VPP RP Transitions and the Command Status Registers
Byte write and block erase completion are not guaranteed if VPP drops below VPPH If the VPP Status bit of the Status Register (SR 3) is set to ``1'' a Clear Status Register command MUST be issued before further byte write block erase attempts are allowed by the WSM Otherwise the Byte Write (SR 4) or Erase (SR 5) Status bits of the Status Register will be set to ``1''s if error is detected RP transitions to VIL during byte write and block erase also abort the operations Data is partially altered in either case and the command sequence must be repeated after normal operation is restored Device poweroff or RP transitions to VIL clear the Status Register to initial value 10000 for the upper 5 bits The Command User Interface latches commands as issued by system software and is not altered by VPP or CE transitions or WSM actions Its state upon powerup after exit from deep powerdown or after VCC transitions below VLKO is Read Array Mode
15
M28F008
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Temperature Under Bias Storage Temperature Voltage on Any Pin (except VCC and VPP) with Respect to GND VPP Program Voltage with Respect to GND during Block Erase Byte Write VCC Supply Voltage with Respect to GND Output Short Circuit Current
b 55 C to a 125 C b 55 C to a 125 C b 65 C to a 125 C
NOTICE This data sheet contains preliminary information on new products in production The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design
b 2 0V to a 7 0V(1)
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
b 2 0V to a 14 0V(1 2) b 2 0V to a 7 0V(1)
100 mA(3)
NOTES 1 Minimum DC voltage is b0 5V on input output pins During transitions this level may undershoot to b2 0V for periods k 20 ns Maximum DC voltage on input output pins is VCC a 0 5V which during transitions may overshoot to VCC a 2 0V for periods k20 ns 2 Maximum DC voltage on VPP may overshoot to a 14 0V for periods k20 ns 3 Output shorted for no more than one second No more than one output shorted at a time
OPERATING CONDITIONS
Symbol TC VCC Parameter Operating Temperature VCC Supply Voltage (10%) Min
b 55
Max
a 125
Unit C V
4 50
5 50
DC CHARACTERISTICS
Symbol Parameter Notes MC28F008 and MF28F008 Min ILI ILO ICCS Input Load Current Output Load Current VCC Standby Current 1 1 13 Max
g1 0
Unit
Test Conditions
mA mA mA mA mA mA
VCC e VCC Max VIN e VCC or GND VCC e VCC Max VOUT e VCC or GND VCC e VCC Max CE e RP e VIH VCC e VCC Max CE e RP e VCC g0 2V RP e GND g0 2V IOUT (RY BY) e 0 mA VCC e VCC Max CE e GND F e 8 MHz IOUT e 0 mA CMOS Inputs VCC e VCC Max CE e VIL F e 8 MHz IOUT e 0 mA TTL Inputs
g10
20 150
ICCD ICCR
VCC Deep Powerdown Current VCC Read Current
1 1
100 35
50
mA
16
M28F008
DC CHARACTERISTICS (Continued)
Symbol Parameter Notes MC28F008 and MF28F008 Min ICCW ICCE ICCES IPPS VCC Byte Write Current VCC Block Erase Current VCC Erase Suspend Current VPP Standby Current 1 1 12 1 Max 30 30 10 mA mA mA mA mA mA mA mA mA V V V V 65 12 6 V V V VCC e VCC Min IOL e 5 8 mA VCC e VCC Min IOH e b 2 5 mA Byte Write In Progress Block Erase In Progress Block Erase Suspended CE e VIH VPP s VCC VPP l VCC RP e GND g0 2V VPP e VPPH Byte Write in Progress VPP e VPPH Block Erase in Progress VPP e VPPH Block Erase Suspended Unit Test Conditions
g15
200 IPPD IPPW IPPE IPPES VIL VIH VOL VOH VPPL VPPH VLKO VPP Deep PowerDown Current VPP Write Current VPP Block Erase Current VPP Erase Suspend Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP during Normal Operations VPP during Erase Write Operations VCC Erase Write Lock Voltage 3 3 4 24 00 11 4 18 1 1 1 1
b0 5
20 30 30 200 08 VCC a 0 5 0 45
20
CAPACITANCE(5)
Symbol CIN COUT
TA e 25 C f e 1 MHz Parameter Typ 6 8 Max 8 12 Unit pF pF Condition VIN e 0V VOUT e 0V
Input Capacitance Output Capacitance
NOTES 1 All currents are in RMS unless otherwise noted 2 ICCES is specified with the device deselected If the M28F008 is read while in Erase Suspend Mode current draw is the sum of ICCES and ICCR 3 Includes RY BY 4 Block Erases Byte Writes are inhibited when VPP e VPPL and not guaranteed in the range between VPPH and VPPL
17
M28F008
AC INPUT OUTPUT REFERENCE WAVEFORM
AC TESTING LOAD CIRCUIT
271232 - 9 AC test inputs are driven at VOH (2 4 VTTL) for a Logic ``1'' and VOL (0 45 VTTL) for a Logic ``0'' Input timing begins at VIH (2 0 VTTL) and VIL (0 8 VTTL) Output timing ends at VIH and VIL Input rise and fall times (10% to 90%) k 10 ns
CL e 100 pF CL Includes Jig Capacitance RL e 3 3 kX
271232 - 10
AC CHARACTERISTICS
Symbol tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tRC tACC tCE tPWH tOE tLZ tHZ tOLZ tDF tOH
Read-Only Operations(1 4)
Notes M28F008-10(4) Min 100 100 2 100 400 2 3 3 3 3 3 0 0 30 0 0 55 0 30 60 0 55 Max M28F008-12(4) Min 120 120 120 400 60 Max Unit ns ns ns ns ns ns ns ns ns ns
Parameter Read Cycle Time Address to Output Display CE to Output Delay RP High to Output Delay OE to Output Delay CE to Output Low Z CE High to Output High Z OE to Output Low Z OE High to Output High Z Output Hold from Addresses CE or OE Change Whichever is First
NOTES 1 See AC Input Output Reference Waveform for timing measurements 2 OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE 3 Sampled not 100% tested 4 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics
18
M28F008
Figure 8 AC Waveform for Read Operations 19
123211- 11
M28F008
AC CHARACTERISTICS
Symbol tAVAV tPHWL tELWL tWLWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHQV1 tWHQV2 tWHGL tQVVL tVPH tWC tPS tCS tWP tVPS tAS tDS tDH tAH tCH tWPH
Write Operations(1 7)
Notes M28F008-10(7) Min 100 2 1 10 40 2 3 4 100 40 40 5 5 10 30 100 56 56 6 03 0 26 0 6 03 0 0 Max M28F008-12(7) Min 120 1 10 40 100 40 40 5 5 10 30 100 Max Unit ns ms ns ns ns ns ns ns ns ns ns ns ms sec ms ns
Parameter Write Cycle Time RP High Recovery to WE Going Low CE Setup to WE Going Low WE Pulse Width VPP Setup to WE Going High Address Setup to WE Going High Data Setup to WE Going High Data Hold from WE High Address Hold from WE High CE Hold from WE High WE Pulse Width High WE High to RY BY Going Low Duration of Byte Write Operation Duration of Block Erase Operation Write Recovery before Read VPP Hold from Valid SRD RY BY High
NOTES 1 Read timing characteristics during erase and byte write operations are the same as during read-only operations Refer to AC Characteristics for Read-Only Operations 2 Sampled not 100% tested 3 Refer to Table 3 for valid AIN for byte write or block erasure 4 Refer to Table 3 for valid DIN for byte write or block erasure 5 The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash memory including byte program and verify (byte write) and block precondition precondition verify erase and erase verify (block erase) 6 Byte write and block erase durations are measured to completion (SR 7 e 1 RY BY e VOH) VPP should be held at VPPH until determination of byte write block erase success (SR 3 4 5 e 0) 7 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics
20
M28F008
BLOCK ERASE AND BYTE WRITE PERFORMANCE
Parameter Block Erase Time Block Write Time Notes 12 12 M28F008-10 Min Typ 16 06 Max 10 21 Min M28F008-12 Typ 16 06 Max 10 21 Unit sec sec
NOTES 1 25 C 12 0 VPP 2 Excludes System-Level Overhead
21
M28F008
Figure 9 AC Waveform for Write Operations 22
271232- 12
M28F008
ALTERNATIVE CE-CONTROLLED WRITES(1)
Symbol tAVAV tPHEL tWLEL tELEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHQV1 tEHQV2 tEHGL tQVVL tVPH tWC tPS tWS tCP tVPS tAS tDS tDH tAH tWH tEPH Parameter Write Cycle Time RP High Recovery to CE Going Low WE Setup to CE Going Low CE Pulse Width VPP Setup to CE Going High Address Setup to CE Going High Data Setup to CE Going High Data Hold from CE High Address Hold from CE High WE Hold from CE High CE Pulse Width High CE High to RY BY Going Low Duration of Byte Write Operation Duration of Block Erase Operation Write Recovery before Read VPP Hold from Valid SRD RY BY High 25 5 5 6 03 0 0 2 3 4 2 Notes M28F008-10(6) Min 100 1 0 50 100 40 40 5 5 0 25 100 6 03 0 0 Max M28F008-12(6) Min 120 1 0 50 100 40 40 5 5 0 25 100 Max Unit ns ms ns ns ns ns ns ns ns ns ns ns ms sec ms ns
NOTES 1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE and WE In systems where CE defines the write pulsewidth (within a longer WE timing waveform) all setup hold and inactive WE times should be measured relative to the CE waveform 2 Sampled not 100% tested 3 Refer to Table 3 for valid AIN for byte write or block erasure 4 Refer to Table 3 for valid DIN for byte write or block erasure 5 Byte write and block erase durations are measured to completion (SR 7 e 1 RY BY e VOH) VPP should be held at VPPH until determination of byte write block erase success (SR 3 4 5 e 0) 6 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics
23
M28F008
Figure 10 Alternate AC Waveform for Write Operations 24
271232- 13
M28F008
ORDERING INFORMATION
M C 2 8 F 0 0 8 1 0
XY
Package C e 40-Pin Sidebrazed DIP F e 42-Lead Flatpack Access Time 10 e 100 ns 12 e 120 ns
ADDITIONAL INFORMATION
Order Number 290435 292094 292095 292099 294011 290412
28F008SA-L Data Sheet AP-359 AP-360 AP-364 ER-27 ER-28 ``28F008SA Hardware Interfacing'' ``28F008SA Software Drivers'' ``28F008SA Automation and Algorithms'' ``The Intel 28F008SA Flash Memory'' ``ETOX III Flash Memory Technology''
25
M28F008
MC28F008 PACKAGE DIMENSIONS
271232 - 15
Symbol a A A1 A2 A3 B B1 C D D2 E E1 e1 eA eB L N S S1 S2 ISSUE 26
Millimeters Min 0 3 30 1 02 2 29 2 03 0 38 1 27 0 23 50 29 48 26 15 24 14 86 2 29 14 99 15 24 3 18 0 76 0 13 0 13 IWS 17 15 4 06 40 1 78 0 030 0 005 0 005 15 75 15 37 2 79 Reference 0 600 0 125 0 30 51 31 Reference 0 600 0 585 0 090 0 590 Max 10 5 51 1 52 3 99 3 66 0 56 Typical Typical 0 009 1 980 1 900 Solid Lid Solid Lid Notes Min 0 0 130 0 040 0 090 0 080 0 015 0 050
Inches Max 10 0 217 0 060 0 157 0 144 0 022 Typical 0 012 2 020 Reference 0 620 0 605 0 110 Reference 0 675 0 160 40 0 070 Typical Solid Lid Solid Lid Notes
M28F008
MF28F008 PACKAGE DIMENSIONS
271232 - 16
Symbol A B C D D2 E E2 E3 e1 H L N Q S S1 ISSUE
Millimeters Min 2 08 0 43 0 13 26 67 25 40 16 00 13 46 0 89 1 14 32 77 7 87 42 1 27 0 23 0 00 IWS 8 90 1 55 1 02 1 27 0 050 0 009 0 000 8 64 16 51 13 97 1 65 1 40 Typical Reference 0 310 42 Max 2 17 0 58 0 25 27 18 Reference 0 630 0 530 0 035 0 045 1 29 Notes Solid Lid Typical Typical Min 0 082 0 017 0 005 1 050 1 000
Inches Max 0 103 0 023 0 010 1 070 Reference 0 650 0 550 0 065 0 055 Typical Reference 0 340 Notes Solid Lid Typical Typical
0 061 0 040 0 050
27
M28F008
REVISION HISTORY
Number -002 Description Revised Extended Cycling Capability to 10K Block Erase Cycles 160K Block Erase Cycles per Chip Changed IPPS Standby current spec from g10 mA to g15 mA Removed typical Block Erase times Number -003 Description PWD renamed RP for JEDEC standardization compatibility Added MF 42-Lead Flatpack Added 100 ns access time specs Combined VPP Standby current and VPP Read current into one VPP Standby condition with two test conditions (DC Characteristics table)
INTEL CORPORATION 2200 Mission College Blvd Santa Clara CA 95052 Tel (408) 765-8080 INTEL CORPORATION (U K ) Ltd Swindon United Kingdom Tel (0793) 696 000 INTEL JAPAN k k Ibaraki-ken Tel 029747-8511
Printed in U S A xxxx 1295 B10M xx xx

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